Capacitor Structure and Method of Forming the Same

ABSTRACT

Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N 2 O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.

BACKGROUND

Many kinds of capacitors such as metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and metal-insulator-metal (MIM) capacitors are used in semiconductor devices. In particular, the MIM capacitor offers reduced electrode resistance with a wide range of applications.

MIM capacitors have been widely used in functional circuits such as mixed signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random access memory (DRAM), embedded DRAM, and logic operation circuits. In system-on-chip applications, different capacitors for different functional circuits have to be integrated on a same chip to serve different purposes. For example, in mixed signal circuits, capacitors are used as decoupling capacitors and high-frequency noise filters. For DRAM and embedded DRAM circuits, capacitors are used for memory storage; while for RF circuits, capacitors are used in oscillators and phase-shift networks for coupling and/or bypassing purposes. For microprocessors, capacitors are used for decoupling. The traditional way to combine these capacitors on a same chip is to fabricate them in different metal layers.

With the capacitors having different functions formed in different metal layers, the capacitors may work under different operation voltages. For example, when used as decoupling capacitors, the capacitors need to be able to sustain high voltages. Therefore, the capacitor insulators need to be thick. In DRAMs, on the other hand, the operation voltage is low, and the capacitors need to be small in order to increase the DRAM cell density. Therefore, the capacitor insulators need to be thin.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1 through 7 are a method of forming a metal-insulator-metal (MIM) capacitor according to an embodiment; and

FIG. 8 is a chart comparing breakdown voltages of samples of a known MIM capacitor and embodiments of MIM capacitors disclosed herein.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.

Embodiments will be described with respect to a specific context, namely a metal-insulator-metal (MIM) capacitor. Other embodiments may also be applied, however, to other capacitors, such as a polysilicon-insulator-polysilicon (PIP) capacitor and others. Applications of concepts disclosed herein include, among others, high voltage applications, voltage decoupling applications, radio frequency (RF) applications, and dynamic random access memory (DRAM) applications.

In FIG. 1, a capacitor bottom metal 12 is formed over a substrate 10. The substrate 10, in an embodiment, is a semiconductor substrate like silicon with various dielectric layers and/or metallization layers formed over the semiconductor substrate. The substrate 10 can be other structures, such as a semiconductor on insulator (SOI), other semiconductor substrates, organic substrates, or the like, and may comprise other materials and/or structures. The capacitor bottom metal 12, in an embodiment, comprises a bottom barrier layer of titanium nitride (TiN), a layer of aluminum copper (AlCu) over the bottom barrier layer, and a top barrier layer of TiN over the layer of AlCu. In other embodiments, the capacitor bottom metal 12 comprises aluminum, copper, titanium, tantalum, tungsten, the like, or a combination thereof, with or without a barrier layer, such as tantalum nitride, tungsten nitride, the like, or a combination thereof, formed thereover. The capacitor bottom metal 12 can be formed by acceptable deposition processes, such as a chemical vapor deposition (CVD), a physical vapor deposition (PVD), the like, or a combination thereof.

In an embodiment, the capacitor bottom metal 12 is treated with a plasma nitrous oxide (N₂O) treatment after the capacitor bottom metal 12 is formed. The N₂O treatment can form a thin dielectric layer 14 on the capacitor bottom metal 12. In an embodiment, such as when the capacitor bottom metal 12 includes a TiN barrier layer, the N₂O treatment forms a titanium oxide (TiO₂) as the thin dielectric layer 14. In other embodiments, the thin dielectric layer 14 can comprise tantalum oxide (Ta₂O₅), or the like. The thin dielectric layer 14 can have a thickness between approximately 10 angstroms (Å) and approximately 40 Å. The nitrous oxide treatment can increase the smoothness of the capacitor bottom metal 12 and can increase the adhesion of subsequently formed layers.

In FIG. 2, a first dielectric layer 16 is deposited over the capacitor bottom metal 12. In an embodiment, the first dielectric layer 16 comprises silicon nitride. In other embodiments, the first dielectric layer 16 can comprise silicon oxide or the like. The first dielectric layer 16 can be deposited using an acceptable deposition process, such as CVD, a furnace deposition, the like, or a combination thereof. In an embodiment where the MIM is to have a capacitance of 2.0 fF, the first dielectric layer 16 can have a thickness, for example, between approximately 140 Å and approximately 160 Å after deposition. As a person having ordinary skill in the art will readily understand, the capacitance of the MIM structure depends in part on the thickness of the dielectric layers.

In FIG. 3, the first dielectric layer 16 is treated with a plasma N₂O treatment, which forms a second dielectric layer 18. In an embodiment, the N₂O treatment forms an oxide layer, such as a silicon oxide (SiO₂), as the second dielectric layer 18. The N₂O treatment is similar to or the same as described with respect to FIG. 1. After the treatment, the first dielectric layer 16 can have a thickness, for example, between approximately 90 Å and approximately 120 Å, and the second dielectric layer 18 can have a thickness, for example, between approximately 15 Å and approximately 30 Å. The silicon oxide of the second dielectric layer 18 generally has a higher bandgap energy than silicon nitride. A thin layer of the silicon oxide interposed between layers of silicon nitride, as will be shown in further detail below, can increase the breakdown voltage of the MIM without significantly affecting the thickness (due to a difference in permittivity of the materials) for a given capacitance value. Embodiments contemplate various materials where a material, such as with as a thin layer, with a higher bandgap energy is interposed between layers of different materials.

In FIG. 4, a third dielectric layer 20 is deposited over the second dielectric layer 18. In an embodiment, the third dielectric layer 20 comprises silicon nitride. In other embodiments, the third dielectric layer 20 can comprise silicon oxide or the like. The third dielectric layer 20 can be deposited using an acceptable deposition process, such as CVD, a furnace deposition, the like, or a combination thereof. The third dielectric layer 20 can have a thickness, for example, between approximately 140 Å and approximately 160 Å after deposition, such as when the MIM capacitor has a capacitance of 2.0 fF. Other embodiments contemplate different thicknesses for different capacitance values.

In FIG. 5, the third dielectric layer 20 is treated with a plasma N₂O treatment, which forms a fourth dielectric layer 22. In an embodiment, the N₂O treatment forms an oxide layer, such as a silicon oxide (SiO₂), as the fourth dielectric layer 22. The N₂O treatment is similar to or the same as described with respect to FIG. 1. After the treatment, the third dielectric layer 20 can have a thickness, for example, between approximately 90 Å and approximately 120 Å, and the fourth dielectric layer 22 can have a thickness, for example, between approximately 15 Å and approximately 30 Å.

In FIG. 6, a capacitor top metal 24 is formed over the fourth dielectric layer 22. The capacitor top metal 24, in an embodiment, comprises layer of AlCu with a barrier layer of TiN formed thereover. In other embodiments, the capacitor top metal 24 comprises aluminum, copper, titanium, tantalum, tungsten, the like, or a combination thereof, with or without a barrier layer, such as tantalum nitride, tungsten nitride, the like, or a combination thereof. The capacitor top metal 24 can be formed by acceptable deposition processes, such as a CVD, PVD, the like, or a combination thereof.

In FIG. 7, the various metals 12 and 24 and dielectric layers 14, 16, 18, 20, and 22 are patterned to form a MIM capacitor. The patterning may be by an acceptable photolithography process and may include multiple etching steps. For example, a hardmask layer can be deposited over the capacitor top metal 24 and patterned into a hardmask using a photoresist and etching. An etch using the hardmask can pattern one or more of the various layers. Due to etch selectivity of the various materials, for example, multiple etch steps and multiple hardmasks may be used in patterning the MIM capacitor. After the MIM capacitor is patterned, a dielectric layer 26, such as a contact etch stop layer (CESL) like a silicon nitride, or a silicon oxide, such as one with a low deposition rate of approximately 640 Å per minute, for example, is conformally formed along sidewalls and a top surface of the MIM capacitor. Other layers, such as dielectric and metallization layers, can be formed over the MIM capacitor.

It should be noted that other configurations of a MIM capacitor are contemplated within the scope of embodiments, and FIG. 7 is an example of a MIM capacitor. For example, the MIM capacitor can have layers that are not all co-extensive, and any layer can extend further from the center of the MIM than an overlying layer. For example, the capacitor bottom metal 12 can extend further than the dielectric layers 16, 18, 20, and 22, and the dielectric layers 16, 18, 20, and 22 can extend further than the capacitor top metal 24. Further, a MIM capacitor can be formed in a cup configuration where a substrate, such as a dielectric layer, is etched to form a recess, and the various layers are conformally formed within the recess. Excess materials of the layers can then be removed, for example, by a chemical mechanical polish (CMP).

Embodiments may achieve higher breakdown voltages than known MIM capacitors. The inventors of the present disclosure have discovered that by treating the various surfaces of a MIM capacitor as discussed above, pin holes between the capacitor top and bottom metals can be minimized, thereby reducing leakage paths. This can increase the reliability of a MIM capacitor and can achieve higher break down voltages.

FIG. 8 is a chart comparing the percentages of samples of MIM capacitors that breakdown at a given voltage. In FIG. 8, points 30 illustrate the percentage of capacitors having a known structure experiencing breakdown at a given voltage, where the sample size is 32 capacitors formed on a wafer. Points 32, 34, and 36 illustrate percentages of capacitors according to embodiments experiencing breakdown at a given voltage. Points 32 have a sample size of 96 capacitors formed on a wafer, where the N₂O treatment was applied for 15 seconds. Points 34 have a sample size of 224 capacitors formed on a wafer, where the N₂O treatment was applied for 5 seconds. Points 36 have a sample size of 224 capacitors formed on a wafer, where the N₂O treatment was applied for 25 seconds. The capacitors in this experiment have silicon nitride, silicon oxide, silicon nitride, silicon oxide as the first dielectric layer 16, second dielectric layer 18, third dielectric layer 20, and fourth dielectric layer 22, respectively, with the second dielectric layer 18 and the fourth dielectric layer 22 being formed by a N₂O plasma treatment, as discussed above. Each of the capacitors is 2.0 femtofarads (fF). As seen from FIG. 8, a breakdown voltage can be increased from approximately 16V to approximately 25V, which is an increase of greater than 50 percent.

An embodiment is a structure comprising a first conductor on a substrate, a first nitride layer over the first conductor, a first oxide layer over the first nitride layer, a second nitride layer over the first oxide layer, and a second conductor over the second nitride layer.

Another embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer.

Another embodiment is a comprising a first conductor on a substrate, a dielectric stack on the first conductor, and a second conductor on the dielectric stack. The dielectric stack comprises alternating nitride and oxide layers. The dielectric stack comprise at least one nitride layer and at least one oxide layer, and the alternating nitride and oxide layers alternate in a direction from the first conductor towards the second conductor.

A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N₂O) treatment to form a first oxide layer on the first nitride layer; forming a second nitride layer over the first oxide layer; and forming a second conductor over the second nitride layer.

Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 

What is claimed is:
 1. A structure comprising: a conductor-insulator-conductor capacitor on a substrate, the conductor-insulator-conductor capacitor comprising: a first conductor on the substrate, a dielectric stack over the first conductor, the dielectric stack comprising a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer, and a second conductor over the dielectric stack.
 2. The structure of claim 1, wherein the dielectric stack further comprises a second oxide layer over the second nitride layer.
 3. The structure of claim 1 further comprising a thin oxide layer between the first conductor and the dielectric stack.
 4. The structure of claim 1, wherein the first conductor comprises a barrier layer, a thin oxide layer being over the barrier layer.
 5. The structure of claim 4, wherein the first conductor comprises aluminum copper (AlCu), the barrier layer comprises titanium nitride (TiN), and the thin oxide layer comprises titanium oxide (TiO).
 6. The structure of claim 1, wherein each of the first nitride layer and the second nitride layer comprises silicon nitride (SiN), and the first oxide layer comprises silicon oxide (SiO).
 7. A structure comprising: a first conductor on a substrate; a dielectric stack on the first conductor, the dielectric stack comprising alternating nitride and oxide layers, the dielectric stack comprising at least one nitride layer and at least one oxide layer; and a second conductor on the dielectric stack, the alternating nitride and oxide layers alternating in a direction from the first conductor towards the second conductor.
 8. The structure of claim 7, wherein the at least one nitride layer comprises two nitride layers, and wherein the at least one oxide layer comprises two oxide layers.
 9. The structure of claim 7 further comprising a thin oxide layer disposed between the first conductor and the dielectric stack.
 10. The structure of claim 7, wherein a first oxide layer of the at least one oxide layer adjoins the second conductor.
 11. The structure of claim 7, wherein the first conductor comprises a barrier layer, the first conductor comprising aluminum copper (AlCu), the barrier layer comprising titanium nitride (TiN), a thin oxide layer comprising titanium oxide (TiO), the thin oxide layer being disposed between the barrier layer and the dielectric stack.
 12. The structure of claim 7, wherein each layer of the at least one nitride layer comprises silicon nitride (SiN), and wherein each layer of the at least one oxide layer comprises silicon oxide (SiO).
 13. A method comprising: forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N₂O) treatment to form a first oxide layer on the first nitride layer; forming a second nitride layer over the first oxide layer; and forming a second conductor over the second nitride layer.
 14. The method of claim 13, wherein the first N₂O treatment includes using a plasma.
 15. The method of claim 13 further comprising treating the second nitride layer with a second nitrous oxide (N₂O) treatment to form a second oxide layer on the second nitride layer, the second conductor being formed over the second oxide layer.
 16. The method of claim 13 further comprising treating the first conductor with a second nitrous oxide (N₂O) treatment to form a thin oxide layer on the first conductor, the first nitride layer being formed over the thin oxide layer.
 17. The method of claim 13, wherein the first conductor comprises a barrier layer.
 18. The method of claim 13, wherein the first nitride layer and the second nitride layer comprises silicon nitride (SiN), and the first oxide layer comprises silicon oxide (SiO).
 19. The method of claim 13, wherein the first conductor comprises aluminum copper (AlCu) and a barrier layer over the aluminum copper, the barrier layer comprising titanium nitride (TiN), and further comprising forming a thin oxide layer over the barrier layer, the thin oxide layer comprising titanium oxide (TiO).
 20. The method of claim 13, further comprising forming a contact etch stop layer over the second conductor. 